Tracking a relative arrival order of events being stored in multiple queues using a counter using most significant bit values

ABSTRACT

An order controller stores each received event in a separate entry in one of at least two queues with a separate counter value set from an arrival order counter at the time of storage, wherein the arrival order counter is incremented after storage of each of the received events and on overflow the arrival order counter wraps back to zero. The order controller calculates an exclusive OR value of a first top bit of a first counter for a first queue from among the at least two queues and a second top bit of a second counter for a second queue from among the at least two queues. The order controller compares the exclusive OR value with a comparator bit to determine whether a first counter value in the first counter was stored before a second counter value in the second counter

TECHNICAL FIELD

The embodiment of the invention relates generally to managing queues andparticularly to tracking a relative arrival order of events being storedin multiple queues using most significant (MSB) values when a countervalue from a counter is stored with each arriving event to indicatearrival order and the counter is incremented with each arriving event,where the counter wraps back to zero on overflow.

DESCRIPTION OF THE RELATED ART

In electronic systems that handle streams of events, one or more queuesare often positioned to store events until the events can be processed.When events arriving in a stream are stored into multiple, separatequeues, if an in-order setting is designated, the events may need to beprocessed from the queues in the same order that the events arrived inthe stream.

BRIEF SUMMARY

In view of the foregoing, there is a need for a method, system, andcomputer program product for calculating a relative arrival order ofevents being stored in multiple queues when a counter value from acounter is stored with each arriving event to indicate arrival order andthe counter is incremented with each arriving event, where the counterwraps back to zero on overflow.

In one embodiment, a method is directed to storing, by an ordercontroller, each received event in a separate entry from among multipleentries in one of at least two queues with a separate counter value setfrom an arrival order counter at the time of storage, wherein thearrival order counter is incremented after storage of each of thereceived events and on overflow the arrival order counter wraps back tozero. The method is directed to calculating, by the order controller, anexclusive OR value of a first top bit of a first counter for a firstqueue from among the at least two queues and a second top bit of asecond counter for a second queue from among the at least two queues.The method is directed to comparing, by the order controller, theexclusive OR value with a comparator bit to determine whether a firstcounter value in the first counter was stored before a second countervalue in the second counter, wherein the result of comparison of theexclusive OR value with the comparator bit determines whether thecounter with the larger value was stored first or whether the counterwith the smaller value was stored first.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The novel features believed characteristic of one or more embodiments ofthe invention are set forth in the appended claims. The one or moreembodiments of the invention itself however, will best be understood byreference to the following detailed description of an illustrativeembodiment when read in conjunction with the accompanying drawings,wherein:

FIG. 1 illustrates a block diagram of one example of an system in whichthe relative arrival order is tracked for events being stored inmultiple queues;

FIG. 2 illustrates a block diagram of one example of components of anorder controller for a multiple queue interface for handling selectionof an available queue for arriving events and tracking the relativearrival order of events placed in one of the multiple queues;

FIG. 3 illustrates a block diagram of one example of values stored witheach queue entry, including an order counter value and a status bit;

FIG. 4 illustrates a block diagram of examples of components of an ordercontroller for a multiple queue interface for handling event selectionof events placed in one of multiple queues to be processed from thequeues in order of arrival;

FIGS. 5A, 5B, 5C, and 5D illustrate a block diagram of one example of anorder controller tracking a relative arrival order of events beingstored in multiple queues when a counter value from a counter is storedwith each arriving event to indicate arrival order and the counter isincremented with each arriving event, where the counter wraps back tozero on overflow;

FIG. 6 illustrates one example of a block diagram of one example of anorder controller tracking a relative arrival order of events beingstored in more than two queues;

FIGS. 7A-7B illustrate one example of a block diagram of an ordercontroller for selecting an oldest event from among more than twoqueues, the relative arrival order of events being stored in more thantwo queues is tracked;

FIG. 8 illustrates a block diagram of one example of a computer systemin which one embodiment of the invention may be implemented;

FIG. 9 illustrates a block diagram of one example of a memory corecontroller including a queue interface with multiple queues in whichevents are placed and in which the relative arrival order of events istracked;

FIG. 10 illustrates a high level logic flowchart of a process andprogram for managing one or more counters and one or more pointers in aqueue interface with multiple queues in which events are placed and inwhich the relative arrival order of events is tracked;

FIG. 11 illustrates a high level logic flowchart of a process andprogram for managing incoming event requests in a queue interface withmultiple queues in which events are placed and in which the relativearrival order of events is tracked; and

FIGS. 12A-12B illustrate a high level logic flowchart of a process andprogram for managing selection of a next event to process in a queueinterface with multiple queues in which events are placed and in whichthe relative arrival order of events is tracked.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of the present invention. It will be apparent, however, toone skilled in the art that the present invention may be practicedwithout these specific details. In other instances, well-knownstructures and devices are shown in block diagram form in order to avoidunnecessarily obscuring the present invention.

In addition, in the following description, for purposes of explanation,numerous systems are described. It is important to note, and it will beapparent to one skilled in the art, that the present invention mayexecute in a variety of systems, including a variety of computer systemsand electronic devices operating any number of different types ofoperating systems.

FIG. 1 illustrates a block diagram of one example of an system in whichthe relative arrival order is tracked for events being stored inmultiple queues.

In the example, a receiving interface 104 receives event stream 102 fromone or more devices. In the example, event stream 102 may represent astream of events arriving in a particular order at receiving interface104 from one or more devices over one or more periods of time. In theexample, receiving interface 104 identifies one or more classificationsof each event received in event stream 102 and selects a queueassociated with each event, based on the classification, from among oneor more queues in a queue interface 110. In one example, receivinginterface 104 may identify whether each event in event stream 102 isclassified as a read request or as a write request. In other examples,receiving interface 104 may identify whether each event in event stream102 is classified as additional or alternate types of requests.

In the example, queue interface 110 includes a queue 106 of a depth of Nentries and a queue 108 of a depth of M entries. In one example, onlyevents classified as read requests in event stream 102 are stored inqueue 106 and only events classified as write requests in event stream102 are stored in queue 108. In other embodiments, queue interface 110may include a single queue or may include additional queues. Forexample, in another embodiment, queue interface 110 may include multiplequeues in which read requests are stored and multiple queues in whichwrite requests are stored. In one embodiment, the depth of N entries ofqueue 106 is equal to the depth of M entries of queue 108. In anotherembodiment, the depth of N entries of queue 106 is not equal to thedepth of M entries of queue 108.

In the example, an order controller 112 may send control signals to andbetween one or more of receiving interface 104, queue interface 110, anda processing interface 114. In another embodiment, one or morecomponents of order controller 112 may be implemented within one or moreinterfaces or order controller 112 may be implemented through multipleseparate controllers.

In one example, order controller 112 controls whether events received inevent stream 102 at receiving interface 104 are rejected or placed in aqueue. In addition, order controller 112 controls the selection of theparticular queue in which a non-rejected event is placed within queueinterface 110. Further, order controller 112 controls tracking of therelative arrival order of each event in each queue by storing a ordercounter value in an order counter register with each event in eachqueue, where the counter value is set by an arrival order counter thatincrements for each event arrival and wraps back to zero on overflow. Inaddition, in the example, order controller 112 controls the selection ofthe next active event from among queue 106 and queue 108 to be processedby processing interface 114 by determining, based on the order countervalues assigned to each next active event entry in queue 106 and queue108, which of the order counter values is the oldest, and marks theselected event entry as no longer active. In one example, ordercontroller 112 determines which of the order counter values assigned toeach of the next active events was stored first, and therefore is theoldest, by performing an exclusive OR operation of the most significantbit (MSB) of the order counter values assigned to the next two activeevents and comparing the exclusive OR value with “0” to determinewhether to select the next active entry stored with the smaller orlarger of the order counter values. In particular, in one example, theMSB may represent the top bit of the arrival order counter value, whichwhen stored as an order counter value may represent an overflow bit forpurposes of tracking the relative arrival order of entries. In theexample, if the exclusive OR value equals “0”, then the order countervalue with the lower bits with the smaller value is the oldest entry,otherwise the order counter value with the lower bits with the largervalue is the oldest entry. By performing an exclusive OR operation ofthe MSB of the order counter values assigned to the next two activeevents and comparing the exclusive OR value with “0” to determine whichcounter value was stored first, the arrival order of the next two activeevents can be tracked from the order counter values stored with theevents, but independent of an actual sequential order shown in the ordercounter values.

In one example, an exclusive OR operation (XOR) is a logical operationthat outputs “true” or “1”, whenever both inputs differ. For example,when the MSBs of the order counter values assigned to the next twoactive events are compared using a exclusive OR operation, if the topbits are the same, such as either both “0” or both “1”, the output ofexclusive OR operation is “0” or “false” and when the top bits aredifferent” the output of the exclusive OR operation is “1” or “true”.

In the example, by performing an exclusive OR operation of the MSBs ofthe order counter values assigned to the next two active events andcomparing the exclusive OR value with “0” to determine whether to selectthe next active entry stored with the smaller or larger of the lowerbits of the order counter values, a counter value alone may be storedwith each event entry to track the relative arrival order of eventsplaced in multiple queues, without necessitating any additional countingof each overflow of a counter and without necessitating a largercounter. In one example, the arrival order counter is set to count to“2(N+M)”, where N is the depth of entries in queue 106 and M is thedepth of entries in queue 108, and where the MSB, or top bit, of thearrival order counter effectively represents an overflow bit forpurposes of tracking the relative arrival order of entries. In anotherexample, where queue interface 110 includes more than two queues, thearrival order counter may be set to count to a value representing 2times the sum of the depths of all the queues and order controller 112may include additional logic for selecting which next activity entry isthe oldest from among each pairing of the queues. In addition, in otherexamples, multiple arrival order counters may be implemented or a singlearrival order counter may be implemented to set order counter valuesacross more than two queues.

FIG. 2 illustrates a block diagram of one example of components of anorder controller for a multiple queue interface for handling selectionof an available queue for arriving events and tracking the relativearrival order of events placed in one of the multiple queues.

In the example, order controller 112 includes, for handling an incomingevent stream, an N entry queue counter 204 set to count N entries and anM entry queue counter 206, set to count M entries, where ordercontroller 112 uses N entry queue counter 204 to count the number ofactive entries in queue 106 and uses M entry queue counter 206 to countthe number of active entries in queue 108.

In the example, order controller 112 includes, for handling an incomingevent stream, an arrival order counter 202. In one example, arrivalorder counter 202 is set to count to a value equal to “2(N+M)−1”, whereN is the number of entries in queue 106 and M is the number of entriesin queue 108. When the count in arrival order counter 202 overflows,arrival order counter 202 wraps back to zero. In the example, arrivalorder counter 202 may be set to count to alternate values.

In the example, a receiving interface controller 210 handles incomingevents in event stream 102. In one example, receiving interfacecontroller 210 handles incoming events in event stream 102 through aclassification detector 212 that identifies a particular classificationfor each event and selects the queue associated with the particularclassification. In one example, a queue status detector 214 detectswhether the entry queue counter for the selected queue, from among Nentry queue counter 204 and M entry queue counter 206, indicates theselected queue is full. In the example, if queue status detector 214detects that the selected queue is full, a full queue handler 216rejects the incoming event. In one example, queue status detector 214efficiently detects whether an incoming entry can be added to a selectedqueue or not by checking whether the counter value in the entry queuecounter for the selected queue is set to a value indicating all theentries are active and the queue is full. As order controller 112selects queue entries for processing by processing interface 114, ordercontroller 112 reduces the count in the entry queue counter associatedwith the queue from which the entry is processed so that the value ineach of N entry queue counter 204 and M entry queue counter 206 reflectsthe current number of active entries in each queue.

In the example, if queue status detector 214 detects that the selectedqueue is not full, an open queue handler 218 controls adding theincoming event as an entry to the selected queue from among queue 106and queue 108 with an order counter value for the entry set to thecurrent counter value set in arrival order counter 202, sets a statusbit for the entry to “active”, increments arrival order counter 202, andincrements the entry queue counter for the selected queue from among Nentry queue counter 204 and M entry queue counter 206. In the example,by setting arrival order counter 202 to count up to “2(N+M)” and bystoring each event entry with an order counter value set to the currentarrival order counter value in arrival order counter 202, the ordercounter value stored with each event entry in each queue allows ordercontroller 112 to efficiently track the relative arrival order of eachentry in each of queue 106 and queue 108 even when arrival order counter202 overflows and wraps back to zero.

FIG. 3 illustrates one example of values stored with each queue entry,including an order counter value and a status bit. In the example, asillustrated at reference numeral 302, each queue entry in queue 106 andqueue 108 may include, but is not limited to, an event register 304 forstoring an event identifier 310, an order counter register 306 of samelength as arrival order counter 202 for storing an order counter value312, and a status bit register 308 for storing a status bit 314 ofone-bit length. In the example, event identifier 310 may include one ormore attributes such as a starting address of the event, a size of thetransaction, and a byte-enable setting. In the example, order countervalue 312 may include the arrival order counter value at the time ofarrival to indicate relative arrival order. In one example, the MSB oforder counter value 312, which may also refer to the top bit of ordercounter value 312, may effectively represent an overflow bit availablefor a first step in determining the relative arrival order of an entryin comparison with another entry, with the other bits of order countervalue 312 effectively representing the counter values available for asecond step in determining the relative arrival order of the entry incomparison with another entry. In one example, where order counter value312 is N bits long, the [0] bit may refer to the top bit and the [1:N]bits may refer to the other bits. In the example, status bit 314 mayinclude a status bit set in a status bit register to indicate whetherthe event is pending, or “active”, or has been processed, or is “done”.In additional or alternate examples, each queue entry, as illustrated atreference numeral 302, may include additional or alternate data.

FIG. 4 illustrates a block diagram of one example of components of anorder controller for a multiple queue interface for handling eventselection of events placed in one of multiple queues to be processedfrom the queues in order of arrival.

In the example, order controller 112 manages a separate front pointerfor each of queue 106 and queue 108. In the example, a front pointer 402points to entries in queue 106 and a front pointer 404 points to entriesin queue 108. Front pointer 402 and front point 404 are initially set tozero and point to the next entry to be handled in each queue. When anentry is released from one of queue 106 and queue 108 to processinginterface 114, the front pointer for the queue is incremented oneposition, to point to the next entry to be handled. In the example, ifeither of front pointer 402 or front pointer 404 points to an entry andthe status bit for the entry is set to “done”, then there are no entriesleft in the queue to be handled.

In the example, order controller 112 may include a processing interfacecontroller 404 for handling selection of the next event to process fromamong the events in queue 106 and queue 108. In the example, asillustrated at reference numeral 406, processing interface controller404 triggers a queue processing selector 408 to determine the next eventto process. In the example, as illustrated at reference numeral 406,once queue processing selector 408 selects an event to be processed,processing interface controller 404 releases the selected event to beprocessed, sets the status bit for the entry for the selected event to“done”, increments the front pointer for the selected event queue fromamong front pointer 402 and front pointer 404, and decrements theselected event entry queue counter from among N entry queue counter 204and M entry queue counter 206.

In the example, queue processing selector 408 may include an availableentry detector 412. Available entry detector 412 examines the status bitassigned to the entry pointed to by each of front pointer 402 and frontpointer 404. As illustrated at reference numeral 414, if both frontpointer 402 and front pointer 404 point to entries with each with astatus bit set to “done”, then no entry is selected for processing. Asillustrated at reference numeral 416, if only one of front pointer 402and front pointer 404 point to an entry with a status bit set to“active”, then the entry pointed to with the status bit set to “active”is selected for processing. As illustrated at reference numeral 418, ifboth front pointer 402 and front pointer 404 each point to an entry witha status bit set to “active”, then an exclusive OR calculator 420 istriggered. Exclusive OR calculator 420 represents logic for performingan exclusive OR operation (XOR) of the MSB of the first N entry queue,front pointer entry, order counter value and MSB of the second M entryqueue, front pointer entry, order counter value, as illustrated atreference numeral 422. In the example, an exclusive OR value is true or“1” if the MSB of the N entry queue order counter value is not the sameas the MSB of the M entry queue order counter value and is false or “0”if the MSB of the N entry queue order counter value is the same as theMSB of the M entry queue order counter value.

In the example, an exclusive OR comparator 430 represents logic forcomparing the exclusive OR value calculated by exclusive OR calculator420 with a comparator bit setting. In one example, as illustrated atreference numeral 432, if the XOR value=“0”, then the front pointerentry with the smaller order counter value is selected. As illustratedat reference numeral 434, if the XOR value=“1”, then the front pointerentry with the larger order counter value is selected. In particular, indetermining which order counter value is smaller or larger, in oneexample, exclusive OR comparator 430 may first compare the [1:N] bits ofeach order counter value and set the comparator bit to “1” if the firstqueue front pointer entry [1:N] bits are larger than the second queuefront pointer entry [1:N] bits and to “0” if the first queue frontpointer entry [1:N] bits are smaller than the second queue front pointerentry [1:N] bits. Exclusive OR comparator 430 may then implementexclusive-not-OR (XNOR) logic to select the oldest counter value, whereif the XNOR computation of the XOR value and the comparator bit is alogical “1”, then the first queue order counter value is older and ifthe XNOR computation of the XOR value and the comparator bit is alogical “0”, then the second queue order counter value is older.

In the example, the XOR gate required for performing the XOR operationof exclusive OR calculator 420 on the MSB counter bits for each pair ofqueues requires a minimal amount of logic to determine whether thesmaller or larger remainder value is older. In the example, thecomparison gate required for performing the comparison operation ofexclusive OR comparator 430 requires a minimal amount of logic todetermine which event is older. In one example, exclusive OR comparator430 may be implemented using a comparator and an XNOR gate. In anexample where the number of queues implemented is greater than twoqueues, in one example, an exclusive OR calculator may be implementedfor each pairing of queues or for only a selection of pairings ofqueues, where by minimizing the logic required for determining whether asmaller or larger entry counter is older for each pairing of queues, thelogic required for exclusive OR comparator 430 to determine which entrycounter is the oldest from among all the queues, is also minimized.

FIGS. 5A, 5B, 5C and 5D illustrate a block diagram of one example of anorder controller tracking a relative arrival order of events beingstored in multiple queues when a counter value from a counter is storedwith each arriving event to indicate arrival order and the counter isincremented with each arriving event, where the counter wraps back tozero on overflow.

In the example, an event stream is illustrated for two queues, where Nis set to a depth of 2 entries and M is set to a depth of 2 entries, asillustrated at reference numeral 500. In the example, as illustrated atreference numeral 502, an arrival order counter set to count [0:2] isset representing a 2(N+M) counter, a first queue (Q1) front pointer, aQ1 entry queue counter, a second queue (Q2) front pointer, and a Q2entry queue counter are all initially set to “0”. In the example, asillustrated in a queue status 504, the front pointer of each of Q1 andQ2 initially points to the entry set to “0”, which is the first entry ineach queue, the order counter value for each entry in each of Q1 and Q2is set to “0” and the status bit for each entry in each of Q1 and Q2 isset to “0”, which is the “done” status bit setting.

In the example, Q1 is designated for storing events classified as “read”events and Q2 is designated for storing events classified as “write”events. In the example, as illustrated in a sequence 506 and a queuestatus 508, an event A arrives, which is classified as a read event andplaced in the first open queue entry of Q1, with the Q1 entry queuecounter incremented to “1”, an event A order counter value set to thecurrent arrival order counter value of “000”, and an event A status bitset to “1”. The arrival order counter is incremented to “001”. Next, asillustrated in sequence 506 and queue status 508, an event B arrives,which is classified as a read event and placed in the next open queueentry of Q1, with the Q1 entry queue counter incremented to “2”, anevent B order counter value set to the current arrival order countervalue of “001”, and an event B status bit set to “1”. The arrival ordercounter is incremented to “010”. Next, as illustrated in sequence 506and queue status 508, and an event C arrives, which is classified as awrite event and placed in the next open queue entry of Q2, with the Q2entry queue counter incremented to “1”, an event C order counter valueset to the current arrival order counter value of “010”, and an event Cstatus bit set to “1”. The arrival order counter is incremented to“011”. Next, as illustrated in sequence 506 and queue status 508, anevent D arrives, which is classified as a write event and placed in thenext open queue entry of Q2, with the Q2 entry queue counter incrementedto “2”, an event D order counter value set to the current arrival ordercounter value of “011”, and an event D status bit set to “1”. Thearrival order counter is incremented to “100”.

In the example, as illustrated in a sequence 510, from among event Apointed to by the Q1 front pointer and event C pointed to by the Q2front pointer, both with status bits set to “active”, event A isselected to be processed. In particular, in the example, an XORoperation is performed on the [0] bit, or top bit, of the event Acounter, which is “0”, with the [0] bit of the event C counter, which is“0”. The XOR value resulting from the operation is a “0”. In theexample, when the XOR value is “0”, then the event with the smallervalue in the remainder bits of the counter, or [1:2] bits of thecounter, is selected. In the example, the event A remainder bits countervalue is “00”, which is smaller than the event C remainder bits countervalue of “10”. As illustrated in sequence 510 and a queue status 512,the event A entry status bit is set to “0”, the Q1 entry queue counteris decremented to “1”, and the Q1 front pointer is incremented to “1”and points to the entry for event C. Next, as illustrated in sequence510 and queue status 512, event E arrives, which is classified as a readevent and placed in the first open entry in Q1, with the Q1 entry queuecounter incremented to “2”, the event E order counter value set to thecurrent arrival order counter value of “100”, and an event E status bitset to “1”. Next, as illustrated in sequence 510, the arrival ordercounter is incremented to “101”.

In the example, as illustrated in a sequence 514, from among event Bpointed to by the Q1 front pointer and event C pointed to by the Q2front pointer, both with status bits set to “1”, event B is selected tobe processed. In particular, in the example, an XOR operation isperformed on the [0] bit of the event B counter, which is “0”, with the[0] bit of the event C counter, which is “0”. The XOR value resultingfrom the operation is a “0”. In the example, when the XOR value is “0”,then the event with the smaller value in the remainder bits of thecounter, or [1:2] bits of the counter, is selected. In the example, theevent B remainder bits counter value is “01”, which is smaller than theevent C remainder bits counter value of “10”. As illustrated in sequence514 and a queue status 516, the event B status bit is set to “0”, the Q1entry queue counter is decremented to “1”, and the Q1 front pointer isincremented to overflow to “0” and points to the entry for event E.

In the example, as illustrated in a sequence 518, from among event Epointed to by the Q1 front pointer and event C pointed to by the Q2front pointer, both with status bits set to “1”, event C is selected tobe processed. In particular, in the example, an XOR operation isperformed on the [0] bit of the event E counter, which is “1”, with the[0] bit of the event C counter, which is “0”. The XOR value resultingfrom the operation is a “1”. In the example, when the XOR value is “1”,then the event with the larger value in the remainder bits of thecounter, or [1:2] bits of the counter, is selected. In the example, theevent C remainder bits counter value is “10”, which is larger than theevent E remainder bits counter value of “00”. As illustrated in sequence518 and a queue status 520, the event C status bit is set to “0”, the Q2entry queue counter is decremented to “1”, and the Q2 front pointer isincremented to “1”, pointing to the entry for event D. Next, asillustrated in sequence 518 and queue status 520, event F arrives, whichis classified as a write event and placed in the first open entry in Q2,with the Q2 entry queue counter incremented back to “2”, the event Forder counter value set to the current arrival order counter value of“101”, and an event F status bit set to “1”. Next, as illustrated insequence 518, the arrival order counter is incremented to “110”.

In the example, as illustrated in a sequence 522, from among event Epointed to by the Q1 front pointer and event D pointed to by the Q2front pointer, both with status bits set to “1”, event D is selected tobe processed. In particular, in the example, an XOR operation isperformed on the [0] bit of the event E counter, which is “1”, with the[0] bit of the event D counter, which is “0”. The XOR value resultingfrom the operation is a “1”. In the example, when the XOR value is “1”,then the event with the larger value in the remainder bits of thecounter, or [1:2] bits of the counter, is selected. In the example, theevent D remainder bits counter value is “11”, which is larger than theevent E remainder bits counter value of “00”. As illustrated in sequence522 and a queue status 524, the Q2 entry queue counter is decremented to“1”, the Q2 front pointer is incremented and overflows to “0”, pointingto the entry for event F. Next, as illustrated in sequence 522 and queuestatus 524, event G arrives, which is classified as a read event andplaced in the first open entry in Q1, with the Q1 entry queue counterincremented back to “2”, the event G order counter value set to thecurrent arrival order counter value of “110”, and an event G status bitset to “1”. Next, as illustrated in sequence 522, the arrival ordercounter is incremented to “111”.

In the example, as illustrated in a sequence 526, from among event Epointed to by the Q1 front pointer and event F pointed to by the Q2front pointer, both with status bits set to “1”, event E is selected tobe processed. In particular, in the example, an XOR operation isperformed on the [0] bit of the event E counter, which is “1”, with the[0] bit of the event F counter, which is “1”. The XOR value resultingfrom the operation is a “0”. In the example, when the XOR value is “0”,then the event with the smaller value in the remainder bits of thecounter, or [1:2] bits of the counter, is selected. In the example, theevent E remainder bits counter value is “00”, which is smaller than theevent F remainder bits counter value of “01”. As illustrated in sequence526 and a queue status 528, the Q1 entry queue counter is decremented to“1”, and the Q1 front pointer is incremented to “1”, pointing to theentry for event G. Next, as illustrated in sequence 526 and queue status528, event H arrives, which is classified as a write event and placed inthe first open entry in Q2, with the Q2 entry queue counter incrementedback to “2”, the event H order counter value set to the current arrivalorder counter value of “111”, and an event H status bit set to “1”.Next, as illustrated in sequence 526, the arrival order counter isincremented to “000”.

In the example, as illustrated in a sequence 530, from among event Gpointed to by the Q1 front pointer and event F pointed to by the Q2front pointer, both with status bits set to “1”, event F is selected tobe processed. In particular, in the example, an XOR operation isperformed on the [0] bit of the event G counter, which is “1”, with the[0] bit of the event F counter, which is “1”. The XOR value resultingfrom the operation is a “0”. In the example, when the XOR value is “0”,then the event with the smaller value in the remainder bits of thecounter, or [1:2] bits of the counter, is selected. In the example, theevent F remainder bits counter value is “01”, which is smaller than theevent G remainder bits counter value of “10”. As illustrated in sequence530 and a queue status 532, the event F status bit is set to “0”, the Q2entry queue counter is decremented to “1”, and the Q2 front pointer isincremented to “1”, pointing to the entry for event H.

In the example, as illustrated in a sequence 534, from among event Gpointed to by the Q1 front pointer and event H pointed to by the Q2front pointer, both with status bits set to “1”, event G is selected tobe processed. In particular, in the example, an XOR operation isperformed on the [0] bit of the event G counter, which is “1”, with the[0] bit of the event H counter, which is “1”. The XOR value resultingfrom the operation is a “0”. In the example, when the XOR value is “0”,then the event with the smaller value in the remainder bits of thecounter, or [1:2] bits of the counter, is selected. In the example, theevent G remainder bits counter value is “10”, which is smaller than theevent H remainder bits counter value of “11”. As illustrated in sequence534 and a queue status 536, the event G status bit is set to “0”, the Q1entry queue counter is decremented to “0”, and the Q1 front pointer isincremented and overflows to “0”. Next, as illustrated in sequence 534and queue status 536, event I arrives, which is classified as a readevent and placed in the first open entry in Q1, with the Q1 entry queuecounter incremented back to “1”, the event I order counter value set tothe current arrival order counter value of “000”, and an event I statusbit set to “1”. Next, as illustrated in sequence 534, the arrival ordercounter is incremented to “001”.

In the example, as illustrated in a sequence 538, from among event Ipointed to by the Q1 front pointer and event H pointed to by the Q2front pointer, both with status bits set to “1”, event H is selected tobe processed. In particular, in the example, an XOR operation isperformed on the [0] bit of the event I counter, which is “0”, with the[0] bit of the event H counter, which is “1”. The XOR value resultingfrom the operation is a “1”. In the example, when the XOR value is “1”,then the event with the larger value in the remainder bits of thecounter, or [1:2] bits of the counter, is selected. In the example, theevent H remainder bits counter value is “11”, which is larger than theevent I remainder bits counter value of “00”. As illustrated in sequence538 and a queue status 540, the event H status bit is set to “0”, the Q2entry queue counter is decremented to “0”, and the Q2 front pointer isincremented and overflows to “0”, pointing to event F, which already hasa status bit set to “done”.

In the example, as illustrated in a sequence 542 and a queue status 544,event I is selected to be processed. In particular, in the example,event I is the only entry with a front pointer set to a status bit setto “active”, therefore event I is selected to be processed, the statusbit for event I is set to “0”, the Q1 entry queue counter is decrementedto “0”, and the Q1 front pointer is incremented to “1”. As illustratedin queue status 542, both the Q1 front pointer and the Q2 front pointerboth point to entries with a status of “0”, therefore there are noentries remaining to be processed in Q1 and Q2.

FIG. 6 illustrates a block diagram of one example of an order controllerfor tracking a relative arrival order of events being stored in morethan two queues. In the example, an event stream is illustrated for fourqueues, where each queue is set to a depth of 2 entries, as illustratedat reference numeral 600.

In the example, as illustrated at reference numeral 602, theinfrastructure for the four queues includes an arrival order counter setto count 2*(number of queues)*(N), which is 2*(4)*2=16. In the example,in order to count 16 bits, the arrival order counter is set to count[0:3] bits. In the example illustrated at reference numeral 602, eachqueue from among a Q1 604, a Q2 606, a Q3 608, and a Q4 610, includes afront pointer for counting which entry is currently the front of eachqueue and an entry queue counter for counting a current number of activeentries in each queue. In additional embodiments, additional oralternate pointers or counters may be implemented to track the currententry in each queue. In the example, each of Q1 604, Q2 606, Q3 608, andQ4 610 track an event identifier and a counter value stored for eachevent. In addition, although not depicted, each entry in each queue mayinclude a status bit indicating whether an entry is active or done.

In the example, each of Q1 604, Q2 606, Q3 608, and Q4 610 are set to adepth of “2” entries, however, for purposes of illustration, an exampleof a history of entries which may be entered in a queue, over time, isillustrated. In particular, in the example, a first event A arrives andis placed in Q1 604, with a counter value set to the arrival ordercounter value of “0000”. In the example, a next event A arrives and isplaced in Q2 606, with a counter value set to the arrival order countervalue of “0001”. In the example, a next event C arrives and is placed inQ3 608, with a counter value set to the arrival order counter value of“0010”. In the example, a next event D arrives and is also placed in Q3608, with a counter value set to the arrival order counter value of“0011”. In the example, a next event E arrives and is placed in Q4 610,with a counter value set to the arrival order counter value of “0100”.In the example, a next event F arrives and is placed in Q2 606, with acounter value set to the arrival order counter value of “0101”. In theexample, a next event G arrives and is placed in Q1 604, with a countervalue set to the arrival order counter value of “0110”. In the example,a next event H arrives and is placed in Q4 610, with a counter value setto the arrival order counter value of “0111”. In the example, a nextevent I arrives and is placed in Q3 608, with a counter value set to thearrival order counter value of “1000”. In the example, a next event Jarrives and is placed in Q4 610, with a counter value set to the arrivalorder counter value of “1001”. In the example, a next event K arrivesand is placed in Q4 610, with a counter value set to the arrival ordercounter value of “1010”. In the example, a next event L arrives and isplaced in Q2 606, with a counter value set to the arrival order countervalue of “1011”. In the example, a next event M arrives and is placed inQ2 608, with a counter value set to the arrival order counter value of“1100”. In the example, a next event N arrives and is placed in Q1 604,with a counter value set to the arrival order counter value of “1101”.In the example, a next event O arrives and is placed in Q1 604, with acounter value set to the arrival order counter value of “1110”. In theexample, a next event P arrives and is placed in Q4 610, with a countervalue set to the arrival order counter value of “1111”. In the example,a next event Q arrives and is placed in Q1 604, with a counter value setto the arrival order counter value of “0000”. In the example, a nextevent R arrives and is placed in Q2 606, with a counter value set to thearrival order counter value of “0001”. In the example, a next event Sarrives and is placed in Q3 608, with a counter value set to the arrivalorder counter value of “0010”. In the example, a next event T arrivesand is placed in Q1 604, with a counter value set to the arrival ordercounter value of “0011”. In the example, a next event U arrives and isplaced in Q2 606, with a counter value set to the arrival order countervalue of “0100”. In the example, a next event V arrives and is placed inQ3 608, with a counter value set to the arrival order counter value of“0101”. In the example, a next event W arrives and is placed in Q3 608,with a counter value set to the arrival order counter value of “0110”.In the example, a next event X arrives and is placed in Q4 610, with acounter value set to the arrival order counter value of “0111”. In theexample, a next event Y arrives and is placed in Q2 606, with a countervalue set to the arrival order counter value of “1000”. In the example,a next event Z arrives and is placed in Q1 604, with a counter value setto the arrival order counter value of “1001”. In the example, a nextevent a arrives and is placed in Q2 606, with a counter value set to thearrival order counter value of “1010”. In the example, a next event barrives and is placed in Q4 610, with a counter value set to the arrivalorder counter value of “1011”.

In the example, as illustrated, by tracking a four bit counter value foreach entry, to indicate the relative arrival order of each entry in fourdifferent queues, a separate exclusive OR operation may be performed onthe top bit, or counter[0] of a selection of pairs of queues, todetermine whether to select the smaller or larger value in the remainderof the counter bits, or counter [1:3], as the oldest for each of theselection of pairs of queues. Next, the oldest of each of the selectionof pairs of queues is filtered to determine the oldest entry from amongthe four queues. In one example, the selection of pairs of queues mayinclude Q1 604 with Q2 606, Q1 604 with Q3 608, Q1 604 with Q4 610, Q2606 with Q3 608, Q2 606 with Q4 610, and Q3 608 with Q4 610, where ifthe first queue in each pair is oldest, a bit is set, and the selectionof set oldest bits from the pairs are used to determine which queue hasthe oldest entry. In other examples, other selections of pairs of queuesmay be implemented.

FIGS. 7A-7B illustrate a block diagram of one example of an ordercontroller for selecting an oldest event from among more than twoqueues, the relative arrival order of events being stored in more thantwo queues is tracked.

In one example, for the four queues illustrated in FIG. 6 as Q1 604, Q2606, Q3 608, and Q4 610, order controller 112 includes a separateselector, such as pair oldest selector 710, specified for each queuepair in selection of queue pairs 720. In one example, the selection ofqueue pairs 720 includes a selector 722 for selecting whether Q1 isolder than Q2, a selector 724 for selecting whether Q1 is older than Q3,a selector 726 for selecting whether Q1 is older than Q4, a selector 728for selecting whether Q2 is older than Q3, a selector 730 for selectingwhether Q2 is older than Q4, and a selector 732 for selecting whether Q3is older than Q4.

In one example, one or more logical components of exclusive ORcalculator 420 and exclusive OR comparator 430 may be embodied in pairoldest selector 710, for each selection of queue pairs. In one example,pair oldest selector 710, when applied as selector 722, may includeinputs of Q1 counter [0:N] and Q2 counter [0:N] and output a logical “1”if Q1 is older than Q2 or a logical “0” if Q1 is not older than Q2. Inone example, exclusive OR calculator 420 may be implemented through anXOR gate 712 that performs an XOR operation on Q1 counter [0] and Q2counter [0]. In one example, XOR gate 712 outputs a logical “0” if Q1counter [0] and Q2 counter [0] are the same value and outputs a logical“1” if Q1 counter [0] and Q2 counter [0] are different values. In oneexample, exclusive OR comparator 430 may be implemented through acomparator 716, which compares Q1 counter [1:N] and Q2 counter [1:N] andoutputs a logical “1” if Q1[1:N] is larger than Q2[1:N] or a logical “0”if Q1[1:N] is smaller than Q2[1:N]. In addition, exclusive OR comparator430 may be implemented through an XNOR gate 714 that performs an XNORoperation the output of XOR gate 712 and the output of comparator 716.In one example, XNOR gate 714 outputs a logical “0” if the output of XORgate 712 and the output of comparator 716 are different and outputs alogical “1” if the output of XOR gate 712 and the output of comparator716 are the same. In one example, XNOR gate 714 outputs a logical “1” ifQ1 is older than Q2 and outputs a logical “0” if Q1 is not older thanQ2.

In one example, a table 718 illustrates the expected output from XNORgate 714 for a combination of outputs from XOR gate 712 and comparator716. In the example, if the output from XOR gate 712 is a logical “0”and the output from comparator 716 is a logical “0”, the output fromXNOR gate 714 is a logical “1”, indicating that Q1 is not older than Q2.In the example, if the output from XOR gate 712 is a logical “0” and theoutput from comparator 716 is a logical “1”, the output from XNOR gate714 is a logical “0”, indicating that Q1 is older than Q2. In theexample, if the output from XOR gate 712 is a logical “1” and the outputfrom comparator 716 is a logical “0”, the output from XNOR gate 714 is alogical “0”, indicating that Q1 is older than Q2. In the example, if theoutput from XOR gate 712 is a logical “1” and the output from comparator716 is a logical “1”, the output from XNOR gate 714 is a logical “1”,indicating that Q1 is not older than Q2.

In the example, order controller 112 includes oldest entry selector 740for comparing the outputs from the selectors in selected queue pairs 720and selecting the oldest queue entry. In one example, oldest entryselector 740 includes an AND gate for each of the queues, where AND gate742 is specified for Q1, AND gate 744 is specified for Q2, AND gate 746is specified for Q3, and AND gate 748 is specified for Q4. In theexample, each of AND gate 742, AND gate 744, AND gate 746, and AND gate748 receives inputs of a separate combination of selector outputs fromselected queue pairs 720. In one example, each of AND gate 742, AND gate744, AND gate 746, and AND gate 748 output a logical “1” if all of theinputs to the AND gate are a logical “1” and output a logical “0” if notall of the inputs to the AND gate are a logical “1”. Only one of ANDgate 742, AND gate 744, AND gate 746, and AND gate 748 is set to alogical “1” for each comparison. The queue associated with the logicalAND gate set to a logical “1” is the oldest entry.

In one example, AND gate 742 receives an input from selector 722, whichis a logical “1” if Q1 is older than Q2, an input from selector 724,which is a logical “1” if Q1 is older than Q3, and an input fromselector 726, which is a logical “1” if Q1 is older than Q4. In theexample, the output from AND gate 742 is a logical “1” if Q1 is olderthan Q2, Q3, and Q4, which occurs if all of the signals output fromselector 722, selector 724, and selector 726 are a logical “1”.

In one example, AND gate 744 receives an input from selector 722inverted by a NOT gate 752, which is a logical “1” if Q1 is not olderthan Q2, an input from selector 728, which is a logical “1” if Q2 isolder than Q3, and an input from selector 730, which is a logical “1” ifQ2 is older than Q4. In the example, the output from AND gate 744 is alogical “1” if Q2 is older than Q1, Q3, and Q4, which occurs if thesignal output from selector 722 is a logical “0”, which is then invertedby NOT gate 752, and the signals output from selector 724 and selector726 are a logical “1”.

In one example, AND gate 746 receives an input from selector 724inverted by a NOT gate 754, which is a logical “1” if Q1 is not olderthan Q3, an input from selector 728 inverted by a NOT gate 756, which isa logical “1” if Q2 is not older than Q3, and an input from selector732, which is a logical “1” if Q3 is older than Q4. In the example, theoutput from AND gate 746 is a logical “1” if Q3 is older than Q1, Q2,and Q4, which occurs if the signal output from selector 724 is a logical“0”, which is then inverted by NOT gate 754, the signal output fromselector 728 is a logical “0”, which is then inverted by NOT gate 756,and the signal output from selector 732 is a logical “1”.

In one example, AND gate 748 receives an input from selector 726inverted by a NOT gate 758, which is a logical “1” if Q1 is not olderthan Q4, an input from selector 730 inverted by a NOT gate 760, which isa logical “1” if Q2 is not older than Q4, and an input from selector 732inverted by a NOT gate 762, which is a logical “1” if Q3 is not olderthan Q4. In the example, the output from AND gate 748 is a logical “1”if Q4 is older than Q1, Q2, and Q3, which occurs if the signal outputfrom selector 726 is a logical “0”, which is then inverted by NOT gate758, the signal output from selector 730 is a logical “0”, which is theninverted by NOT gate 760, and the signal output from selector 732 is alogical “0”, which is then inverted by NOT gate 726.

In the example, while oldest entry selector 742 is illustrated asincluded multiple AND gates for selecting an oldest queue based oncombinations of inputs from selections of selected queue pairs 720, inadditional or alternate embodiments, other types of logic may beimplemented to select an oldest entry based on the outputs from selectedqueue pairs 720. In one example, oldest entry selector 742 may include acomparator with a table of selection patterns each associated with aparticular queue, where the outputs of selected queue pairs 720 arecompared with the entries in the table of selection patterns to identifya matching selection pattern and identify the oldest entry as the entryfrom the particular queue associated with the matching selectionpattern.

In one example, a multiplexor 770 or other selection logic may beimplemented to receive the outputs of the AND gates of oldest entryselector 740 as inputs for selecting an oldest entry. In one example,multiplexor 770 receives inputs of the [1:N] bits of the counters foreach of Q1, Q2, Q3, and Q4 and selects which of the inputs to output asthe oldest entry based on the signals output by the AND gates of oldestentry selector 740 indicating which queue has the oldest entry. In theexample, if the “Q1 is oldest” signal output by AND gate 742 is alogical “1”, then multiplexor 770 outputs Q1[1:N] as the oldest entry.In the example, if the “Q2 is oldest” signal output by AND gate 744 is alogical “1”, then multiplexor 770 outputs Q2[1:N] as the oldest entry.In the example, if the “Q3 is oldest” signal output by AND gate 746 is alogical “1”, then multiplexor 770 outputs Q3[1:N] as the oldest entry.In the example, if the “Q4 is oldest” signal output by AND gate 748 is alogical “1”, then multiplexor 770 outputs Q4[1:N] as the oldest entry.

In one example illustrated in FIGS. 7A-7B, order controller 112determines the oldest event from among the first entries pointed towithin Q1 604, Q2 606, Q3 608, and Q4 610, which are labeled as event A,event B, event C, and event E.

In the example for event A, event B, event C and event E, selector 722performs an XOR operation on counter [0] for event A of “0” with counter[0] for event B of “0”, yielding an XOR value of a logical “0”, performsa comparison of counter [1:3] for event A of “000” with counter [1:3]for event B of “001”, yielding a logical “0” because “000” is smallerthan “001”, and performs an XNOR operation on the XOR output of logical“0” and the comparator output of logical “0”, yielding a logical “1”,indicating that event A is older than event B.

In addition, in the example for event A, event B, event C and event E,selector 724 performs an XOR operation on counter [0] for event A of “0”with counter [0] for event C of “0”, yielding an XOR value of a logical“0”, performs a comparison of counter [1:3] for event A of “000” withcounter [1:3] for event C of “010”, yielding a logical “0” because “000”is smaller than “010”, and performs an XNOR operation on the XOR outputof logical “0” and the comparator output of logical “0”, yielding alogical “1”, indicating that event A is older than event C.

In addition, in the example for event A, event B, event C and event E,selector 726 performs an XOR operation on counter [0] for event A of “0”with counter [0] for event E of “0”, yielding an XOR value of a logical“0”, performs a comparison of counter [1:3] for event A of “000” withcounter [1:3] for event E of “100”, yielding a logical “0” because “000”is smaller than “100”, and performs an XNOR operation on the XOR outputof logical “0” and the comparator output of logical “0”, yielding alogical “1”, indicating that event A is older than event E.

In addition, in the example for event A, event B, event C and event E,selector 728 performs an XOR operation on counter [0] for event B of “0”with counter [0] of event C of “0”, yielding an XOR value of a logical“0”, performs a comparison of counter [1:3] for event B of “001” withcounter [1:3] for event C of “010”, yielding a logical “0” because “001”is smaller than “010”, and performs an XNOR operation on the XOR outputof logical “0” and the comparator output of logical “0”, yielding alogical “1”, indicating that event B is older than event C.

In addition, in the example for event A, event B, event C and event E,selector 730 performs an XOR operation on counter [0] for event B of “0”with counter [0] of event E of “0”, yielding an XOR value of a logical“0”, performs a comparison of counter [1:3] for event B of “001” withcounter [1:3] for event E of “100”, yielding a logical “0” because “001”is smaller than “100”, and performs an XNOR operation on the XOR outputof logical “0” and the comparator output of logical “0”, yielding alogical “1”, indicating that event B is older than event E.

In addition, in the example for event A, event B, event C and event E,selector 732 performs an XOR operation on counter [0] for event C of “0”with counter [0] of event E of “0”, yielding an XOR value of a logical“0”, performs a comparison of counter [1:3] for event C of “010” withcounter [1:3] for event E of “100”, yielding a logical “0” because “010”is smaller than “100”, and performs an XNOR operation on the XOR outputof logical “0” and the comparator output of logical “0”, yielding alogical “1”, indicating that event C is older than event E.

In the example for event A, event B, event C and event E, AND gate 742receives the outputs of selector 722, selector 724, and selector 726,which are all set to a logical “1”. Because all the inputs to AND gate742 are set to a logical “1”, AND gate 742 is outputs a logical “1”,indicating that Q1, which holds event A, is the oldest.

In the example for event A, event B, event C and event E, AND gate 744receives the outputs of selector 722 inverted by NOT gate 752 and set toa logical “0”, selector 728 set to a logical “1” and selector 730 set toa logical “1”. Because not all the inputs to AND gate 744 are set to alogical “1”, AND gate 744 outputs a logical “0”, indicating that Q2,which holds event B, is not the oldest.

In the example for event A, event B, event C and event E, AND gate 746receives the outputs of selector 724 inverted by NOT gate 754 and set toa logical “0”, selector 728 inverted by NOT gate 756 and set to alogical “0”, and selector 732 set to a logical “1”. Because not all theinputs to AND gate 746 are set to a logical “1”, AND gate 746 outputs alogical “0”, indicating that Q3, which holds event C, is not the oldest.

In the example for event A, event B, event C and event E, AND gate 748receives the outputs of selector 726 inverted by NOT gate 758 and set toa logical “0”, selector 730 inverted by NOT gate 760 and set to alogical “0”, and selector 732 inverted by NOT gate 762 and set to alogical “0”. Because not all the inputs to AND gate 748 are set to alogical “1”, AND gate 748 outputs a logical “0”, indicating that Q4,which holds event E, is not the oldest.

FIG. 8 illustrates a block diagram of one example of a computer systemin which one embodiment of the invention may be implemented. The presentinvention may be performed in a variety of systems and combinations ofsystems, made up of functional components, such as the functionalcomponents described with reference to a computer system 800 and may becommunicatively connected to a network, such as network 802.

Computer system 800 includes a bus 822 or other communication device forcommunicating information within computer system 800, and at least onehardware processing device, such as processor 812, coupled to bus 822for processing information. Bus 822 preferably includes low-latency andhigher latency paths that are connected by bridges and adapters andcontrolled within computer system 800 by multiple bus controllers. Whenimplemented as a server or node, computer system 800 may includemultiple processors designed to improve network servicing power. Wheremultiple processors share bus 822, additional controllers (not depicted)for managing bus access and locks may be implemented.

Processor 812 may be at least one general-purpose processor such as IBM®PowerPC® processor that, during normal operation, processes data underthe control of software 850, which may include at least one ofapplication software, an operating system, middleware, and other codeand computer executable programs accessible from a dynamic storagedevice such as random access memory (RAM) 814, a static storage devicesuch as Read Only Memory (ROM) 816, a data storage device, such as massstorage device 818, or other data storage medium. Software 850 mayinclude, but is not limited to, code, applications, protocols,interfaces, and processes for controlling one or more systems within anetwork including, but not limited to, an adapter, a switch, a server, acluster system, and a grid environment.

Computer system 800 may communicate with a remote computer, such asserver 840, or a remote client. In one example, server 840 may beconnected to computer system 800 through any type of network, such asnetwork 802, through a communication interface, such as networkinterface 832, or over a network link that may be connected, forexample, to network 802.

In the example, multiple systems within a network environment may becommunicatively connected via network 802, which is the medium used toprovide communications links between various devices and computersystems communicatively connected. Network 802 may include permanentconnections such as wire or fiber optics cables and temporaryconnections made through telephone connections and wireless transmissionconnections, for example, and may include routers, switches, gatewaysand other hardware to enable a communication channel between the systemsconnected via network 802. Network 802 may represent one or more ofpacket-switching based networks, telephony based networks, broadcasttelevision networks, local area and wire area networks, public networks,and restricted networks.

Network 802 and the systems communicatively connected to computer 800via network 802 may implement one or more layers of one or more types ofnetwork protocol stacks which may include one or more of a physicallayer, a link layer, a network layer, a transport layer, a presentationlayer, and an application layer. For example, network 802 may implementone or more of the Transmission Control Protocol/Internet Protocol(TCP/IP) protocol stack or an Open Systems Interconnection (OSI)protocol stack. In addition, for example, network 802 may represent theworldwide collection of networks and gateways that use the TCP/IP suiteof protocols to communicate with one another. Network 802 may implementa secure HTTP protocol layer or other security protocol for securingcommunications between systems.

In the example, network interface 832 includes an adapter 834 forconnecting computer system 800 to network 802 through a link and forcommunicatively connecting computer system 800 to server 840 or othercomputing systems via network 802. Although not depicted, networkinterface 832 may include additional software, such as device drivers,additional hardware and other controllers that enable communication.When implemented as a server, computer system 800 may include multiplecommunication interfaces accessible via multiple peripheral componentinterconnect (PCI) bus bridges connected to an input/output controller,for example. In this manner, computer system 800 allows connections tomultiple clients via multiple separate ports and each port may alsosupport multiple connections to multiple clients.

In one embodiment, the operations performed by processor 812 may controlthe operations of flowchart of FIGS. 10, 11, and 12 a-12 b and otheroperations described herein. Operations performed by processor 812 maybe requested by software 850 or other code or the steps of oneembodiment of the invention might be performed by specific hardwarecomponents that contain hardwired logic for performing the steps, or byany combination of programmed computer components and custom hardwarecomponents. In one embodiment, one or more components of computer system800, or other components, which may be integrated into one or morecomponents of computer system 800, may contain hardwired logic forperforming the operations of flowcharts FIGS. 10, 11, and 12 a-12 b.

In addition, computer system 800 may include multiple peripheralcomponents that facilitate input and output. These peripheral componentsare connected to multiple controllers, adapters, and expansion slots,such as input/output (I/O) interface 826, coupled to one of the multiplelevels of bus 822. For example, input device 824 may include, forexample, a microphone, a video capture device, an image scanning system,a keyboard, a mouse, or other input peripheral device, communicativelyenabled on bus 822 via I/O interface 826 controlling inputs. Inaddition, for example, output device 820 communicatively enabled on bus822 via I/O interface 826 for controlling outputs may include, forexample, one or more graphical display devices, audio speakers, andtactile detectable output interfaces, but may also include other outputinterfaces. In alternate embodiments of the present invention,additional or alternate input and output peripheral components may beadded.

With respect to FIG. 8, the present invention may be a system, a method,and/or a computer program product. The computer program product mayinclude a computer readable storage medium (or media) having computerreadable program instructions thereon for causing a processor to carryout aspects of the present invention.

The computer readable storage medium can be a tangible device that canretain and store instructions for use by an instruction executiondevice. The computer readable storage medium may be, for example, but isnot limited to, an electronic storage device, a magnetic storage device,an optical storage device, an electromagnetic storage device, asemiconductor storage device, or any suitable combination of theforegoing. A non-exhaustive list of more specific examples of thecomputer readable storage medium includes the following: a portablecomputer diskette, a hard disk, a random access memory (RAM), aread-only memory (ROM), an erasable programmable read-only memory (EPROMor Flash memory), a static random access memory (SRAM), a portablecompact disc read-only memory (CD-ROM), a digital versatile disk (DVD),a memory stick, a floppy disk, a mechanically encoded device such aspunch-cards or raised structures in a groove having instructionsrecorded thereon, and any suitable combination of the foregoing. Acomputer readable storage medium, as used herein, is not to be construedas being transitory signals per se, such as radio waves or other freelypropagating electromagnetic waves, electromagnetic waves propagatingthrough a waveguide or other transmission media (e.g., light pulsespassing through a fiber-optic cable), or electrical signals transmittedthrough a wire.

Computer readable program instructions described herein can bedownloaded to respective computing/processing devices from a computerreadable storage medium or to an external computer or external storagedevice via a network, for example, the Internet, a local area network, awide area network and/or a wireless network. The network may comprisecopper transmission cables, optical transmission fibers, wirelesstransmission, routers, firewalls, switches, gateway computers and/oredge servers. A network adapter card or network interface in eachcomputing/processing device receives computer readable programinstructions from the network and forwards the computer readable programinstructions for storage in a computer readable storage medium withinthe respective computing/processing device.

Computer readable program instructions for carrying out operations ofthe present invention may be assembler instructions,instruction-set-architecture (ISA) instructions, machine instructions,machine dependent instructions, microcode, firmware instructions,state-setting data, or either source code or object code written in anycombination of one or more programming languages, including an objectoriented programming language such as Smalltalk, C++ or the like, andconventional procedural programming languages, such as the “C”programming language or similar programming languages. The computerreadable program instructions may execute entirely on the user'scomputer, partly on the user's computer, as a stand-alone softwarepackage, partly on the user's computer and partly on a remote computeror entirely on the remote computer or server. In the latter scenario,the remote computer may be connected to the user's computer through anytype of network, including a local area network (LAN) or a wide areanetwork (WAN), or the connection may be made to an external computer(for example, through the Internet using an Internet Service Provider).In some embodiments, electronic circuitry including, for example,programmable logic circuitry, field-programmable gate arrays (FPGA), orprogrammable logic arrays (PLA) may execute the computer readableprogram instructions by utilizing state information of the computerreadable program instructions to personalize the electronic circuitry,in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems), and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer readable program instructions.

These computer readable program instructions may be provided to aprocessor of a general purpose computer, special purpose computer, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, create means forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks. These computer readable program instructionsmay also be stored in a computer readable storage medium that can directa computer, a programmable data processing apparatus, and/or otherdevices to function in a particular manner, such that the computerreadable storage medium having instructions stored therein comprises anarticle of manufacture including instructions which implement aspects ofthe function/act specified in the flowchart and/or block diagram blockor blocks.

The computer readable program instructions may also be loaded onto acomputer, other programmable data processing apparatus, or other deviceto cause a series of operational steps to be performed on the computer,other programmable apparatus or other device to produce a computerimplemented process, such that the instructions which execute on thecomputer, other programmable apparatus, or other device implement thefunctions/acts specified in the flowchart and/or block diagram block orblocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods, and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof instructions, which comprises one or more executable instructions forimplementing the specified logical function(s). In some alternativeimplementations, the functions noted in the block may occur out of theorder noted in the figures. For example, two blocks shown in successionmay, in fact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts or carry out combinations of special purpose hardwareand computer instructions.

Those of ordinary skill in the art will appreciate that the hardwaredepicted in FIG. 8 may vary. Furthermore, those of ordinary skill in theart will appreciate that the depicted example is not meant to implyarchitectural limitations with respect to the present invention.

FIG. 9 is one example of a block diagram of a memory core controllerincluding a queue interface with multiple queues in which events areplaced and in which the relative arrival order of events is tracked.

In the example, a system 900 includes a memory core controller 920 thatprovides a mechanism to attach and interface one or more devices, suchas a master device 910, a slave device 912, and a master device 914 toone or more external memory chips 924. In one example, master device910, slave device 912, and master device 914 may include one or more ofa processor local bus (PLB) master, PLB slave, a direct memory access(DMA) master, DMA slave, and an I/O master. In the example, an arbiter916 interfaces with master device 910, slave device 912, and masterdevice 914 and manages communications between each of the devices andmemory core controller 920. In the example, the communications betweeneach of the devices and memory core controller 920 may include writeevent requests, with a write command and write data, and read eventrequests, with a read command and read data. In the example, an externalmemory interface 922 interfaces between memory core controller 920 andone or more external memory chips 924. In one example, external memoryinterface 922 represents one or more double data rate (DDR), DDR2, andDDR3 synchronous dynamic random-access memory (SDRAM) interfaces andexternal memory chips 924 represents one or more DDR SDRAM, DDR2 SDRAM,and DDR3 SDRAM memories. External memory interface 922 may includedrivers and receivers and may interface with a clock buffer betweenexternal memory interface 922 and external memory chips 924. Inadditional or alternate examples, external memory interface 922 mayrepresent one or more interfaces for one or more additional or alternatetypes of memories and external memory 924 may represent one or moreadditional or alternate types of memories.

In the example, memory core controller 920 may provide a bridge betweenmaster device 910, slave device 912, and master device 914 and externalmemory chips 924 by managing read events requesting data from externalmemory 924 and write events requesting data be written to externalmemory 924. In one example, receiver interface 104 includes a decoder932 for receiving commands from arbiter 916, identifying whether eachcommand is a read command or a write command, and placing identifiedread commands in read request queue 938 and identified write commands ina write request queue 936, where queue interface 110 includes readrequest queue 938 and write request queue 936. In the example,processing interface 114 includes a write buffer 942 for buffering writedata from arbiter 916, a read buffer 950 for buffering read data to beread by arbiter 916, a write control 944 for performing write controllogic for arbiter 916, a read control 946 for performing read controllogic for arbiter 916, a returned read data queue 948 for trackingreturned read data from external memory interface 922, and a memoryinterface block 952 for interfacing with external memory interface 922.

In the example, memory core controller 920 includes order controller112, as logic distributed throughout the components of memory corecontroller 920 for controlling the placement of commands received fromarbiter 916 into read request queue 938 and write request queue 936 andfor controlling the selection of commands to be processed next byexternal memory interface 922 from read request queue 938 and writerequest queue 938. In one example, the command to be processed next fromread request queue and write request queue 938 is selected and passed tomemory interface block 952 for processing by external memory interface922.

FIG. 10 illustrates a high level logic flowchart of a process andprogram for managing one or more counters and one or more pointers in aqueue interface with multiple queues in which events are placed and inwhich the relative arrival order of events is tracked. In the example,the process starts at block 1000 and thereafter proceeds to block 1002.Block 1002 illustrates initializing the front pointer and entry queuecounter of each queue to “0” and setting all status bits in the queuesto “done”. Next, block 1004 illustrates initializing the arrival ordercounter to “0”. Thereafter, block 1006 illustrates a determinationwhether an entry from among the multiple queues is selected forprocessing. At block 1006, if no entry is selected for processing, theprocess passes to block 1012. Block 1012 illustrates a determinationwhether a sequence reset is selected. At block 1012, if a sequence resetis selected, then the process returns to block 1002 and the pointers andcounters are reset. At block 1012, if a sequence reset is not selected,then the process returns to block 1006.

Returning to block 1006, at block 1006, if an entry is selected forprocessing, then the process passes to block 1008. Block 1008illustrates setting the status bit for the selected entry to “done”.Next, block 1010 illustrates incrementing the front pointer in theselected entry queue to point to the next entry in the queue, wrappingback to the first entry on overflow, and the process returns to block1006.

FIG. 11 illustrates a high level logic flowchart of a process andprogram for managing incoming event requests in a queue interface withmultiple queues in which events are placed and in which the relativearrival order of events is tracked. In the example, the process startsat block 1100 and thereafter proceeds to block 1102. Block 1102illustrates a determination whether an incoming event request isdetected. At block 1102, if an incoming event request is detected, thenthe process passes to block 1104. Block 1104 illustrates identifying anevent characteristic for the incoming event request. Next, block 1106illustrates a determination of whether the event queue associated withthe event characteristic is full. At block 1106, if the event queueassociated with the event characteristic is full, then the processpasses to block 1108. Block 1108 illustrates rejecting the incomingevent request, and the process ends.

Returning to block 1106, at block 1106, if the event queue associatedwith the event characteristic is not full, then the process passes toblock 1110. Block 1110 illustrates incrementing the entry queue counterfor the selected queue. Thereafter, block 1112 illustrates inserting anentry for the event request in the selected event queue. Next, block1114 illustrates setting the status bit for the new entry to “active”.Thereafter, block 1116 illustrates setting the counter for the new entryto the current arrival order counter value. Next, block 1118 illustratesincrementing the arrival order counter value” then wrapping back to 0 onoverflow, and the process ends.

FIGS. 12A-12B illustrate a high level logic flowchart of a process andprogram for managing selection of a next event to process in a queueinterface with multiple queues in which events are placed and in whichthe relative arrival order of events is tracked. In the example, theprocess starts at block 1200 and thereafter proceeds to block 1202.Block 1202 illustrates a determination whether the order controller isready to select the next event to process. At block 1202, if the ordercontroller is ready to select the next event to process, then theprocess passes to block 1204. Block 1204 illustrates a determinationwhether the entry pointed to by the front pointer in each queue has astatus bit set to “active”. At block 1204, if the entry pointed to bythe front pointer in each queue has a status bit set to “active”, thenthe process passes to block 1220. Block 1220 illustrates a determinationwhether one of the entries pointed to by the front pointer in one of thequeues has a status bit set to “active”. At block 1220, if only one ofthe entries pointed to by the front pointer in one of the queues has astatus bit set to “active”, then the process passes to block 1224. Block1224 illustrates selecting the event from the entry pointed to with astatus bit set to “active” as the next event to process, and the processends. Returning to block 1220, at block 1220, if none of the entriespointed to by the front pointers in the queues have a status bit set to“active”, then the process passes to block 1222. Block 1222 illustratessetting an indicator of no pending events in the queue, and the processends.

Returning to block 1204, if the entry pointed to by the front pointer ineach queue has a status bit set to “active”, then the process passes toblock 1226. Block 1226 illustrates a determination whether more than twoqueues are implemented for tracking events. At block 1226, if the numberof queues implemented for tracking events is not more than two queues,then the process passes to block 1206.

Block 1206 illustrates calculating the exclusive OR of the MSB of thethe first order counter value pointed to by the first queue frontpointer and the MSB of the second order counter value pointed to by thesecond queue front pointer. Next, block 1208 illustrates a determinationwhether the exclusive OR value is equal to “0”. At block 1208, if theexclusive OR value is equal to “0”, where the comparator bit is set to“0”, then the process passes to block 1210. Block 1210 illustratesselecting the event from the entry pointed to with the 1:N bits of theorder counter with the smaller value, and the process passes to block1214. Returning to block 1208, if the exclusive OR result is not equalto “0”, then the process passes to block 1212. Block 1212 illustratesselecting the event from the entry pointed to with the order counterwith the larger value, and the process passes to block 1214.

Block 1214 illustrates setting the status bit for the selected entry to“done”. Next, block 1216 illustrates incrementing the queue pointer forthe selected event queue. Thereafter, block 1218 illustratesdecrementing the entry queue counter for the selected event queue, andthe process ends.

Returning to block 1226, at block 1226, if more than two queues areimplemented for tracking events, then the process passes to block 1230.Block 1230 illustrates, for a selection of pair of queues, for eachpair, performing the process illustrated in block 1232, block 1234 andblock 1236. Block 1232 illustrates calculating the exclusive OR of theMSB of the first order counter value pointed to by the first queue frontpointer in the pair with the MSB of the second order counter valuepointed to by the second queue front pointer in the pair. Next, block1234 illustrates calculating a comparator value for the 1:N bits of thefirst order counter value compared with the 1:N bits of the second ordercounter value, wherein the comparator value is a logical “1” if the 1:Nbits of the first order counter value are larger than the 1:N bits ofthe second order counter value. Next, block 1236 illustrates calculatingthe XNOR of the exclusive OR of the MSB bits and the comparator value,wherein the XNOR output is a logical “1” if the first order countervalue is older than the second order counter value.

Next, block 1238 illustrates, for each queue, calculating the logicalAND of a combination of a selection of the XNOR outputs for the pairs,wherein only the logical AND gate for the oldest queue outputs a logical“1”. Thereafter, block 1240 illustrates selecting the event from theentry pointed to in the queue identifiers as the oldest queue associatedwith the AND gate that outputs a logical “1”, and the process ends.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising”, when used in this specification specify thepresence of stated features, integers, steps, operations, elements,and/or components, but not preclude the presence or addition of one ormore other features, integers, steps, operations, elements, components,and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the one or more embodiments of the invention has beenpresented for purposes of illustration and description, but is notintended to be exhaustive or limited to the invention in the formdisclosed. Many modifications and variations will be apparent to thoseof ordinary skill in the art without departing from the scope and spiritof the invention. The embodiment was chosen and described in order tobest explain the principles of the invention and the practicalapplication, and to enable others of ordinary skill in the art tounderstand the invention for various embodiments with variousmodifications as are suited to the particular use contemplated.

While the invention has been particularly shown and described withreference to one or more embodiments, it will be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit and scope of the invention.

1. A method for tracking a relative arrival order of a plurality ofevents stored in at least two queues, the method comprising: storing, byan order controller, each of a plurality of received events in aseparate entry from among a plurality of entries in one of at least twoqueues with a separate counter value set from an arrival order counterat the time of storage, wherein the arrival order counter is incrementedafter storage of each of the plurality of received events and onoverflow the arrival order counter wraps back to zero; calculating, bythe order controller, an exclusive OR value of a first top bit of afirst counter for a first queue from among the at least two queues and asecond top bit of a second counter for a second queue from among the atleast two queues; and comparing, by the order controller, the exclusiveOR value with a comparator bit to determine whether a first countervalue in the first counter was stored before a second counter value inthe second counter.
 2. The method according to claim 1, whereincomparing, by the order controller, the exclusive OR value with acomparator bit to determine whether a first counter value in the firstcounter was stored before a second counter value in the second counter,further comprises: responsive to the exclusive OR value matching thecomparator bit, selecting, by the order controller, a smaller value of afirst remainder of bits of the first counter value and a secondremainder of bits of the second counter value as a selected value;responsive to the exclusive OR value not matching the comparator bit,selecting, by the order controller, a larger value of the firstremainder of bits of the first counter value and the second remainder ofbits of the second counter value as the selected value; and selecting,by the order controller, a particular entry stored with the selectedvalue for processing next.
 3. The method according to claim 2, furthercomprising: responsive to selecting the particular entry for processingnext, setting a status bit stored with the particular entry from anactive bit to a done bit and incrementing a pointer to point to a nextentry in a particular queue from among the at least two queues with theparticular entry.
 4. The method according to claim 1, furthercomprising: for a plurality of queues greater than two queues, for eachof a selection of pairings of the plurality of queues from among aplurality of selections of pairings of the plurality of queues:calculating the exclusive OR value of the first top bit of the firstcounter for the first queue from among each pairing of the plurality ofqueues and the second top bit of the second counter for the second queuefrom among each pairing of the plurality of queues, wherein theexclusive OR value is a logical 1 if the first top bit and the secondtop bit are not a same value; comparing, by a comparator, a firstremainder of bits of the first counter with a second remainder of bitsof the second counter to determine whether first remainder of bits islarger than the second remainder of bits, wherein the comparator outputsa logical 1 if the first remainder of bits is larger than the secondremainder of bits; and calculating an exclusive not OR value of theexclusive OR value and the output of the comparator, wherein theexclusive NOT OR value is a logical 1 if the exclusive OR value and theoutput of the comparator are a same value, wherein the exclusive NOT orvalue is a logical 1 if the first counter is older than the secondcounter; for each queue from among the plurality of queues, calculatinga separate logical AND value from among a plurality of logical ANDvalues of a separate logical combination of a separate selection ofoutputs from among the plurality of selection of pairings, wherein onlyone of the plurality of logical AND values calculates a logical “1”indicating on oldest queue; selecting, as an oldest entry from among theplurality of queues, a particular entry from a particular queueassociated with the only one of the plurality of logical AND values thatcalculates a logical “1.
 5. The method according to claim 1, furthercomprising: incrementing, by the order controller, the arrival ordercounter up to a maximum counter value of a number of entries in thefirst queue summed with a number of entries in the second queue less onebefore overflowing and wrapping back to zero.
 6. The method according toclaim 1, further comprising: receiving each of the plurality of receivedevents at a receiving interface of the an order controller; determining,by the order controller, a particular classification from among aplurality of event classifications of a particular event from among theplurality of received events; determining, by the order controller, if aparticular queue from among the at least two queues associated with theparticular classification is full; if the particular queue is full,rejecting, by the order controller, the particular event; if theparticular queue is not full, storing, by the order controller, theparticular event in the particular queue with a current value counted toin the order counter; and incrementing, by the order controller, thearrival order counter.
 7. The method according to claim 6, whereindetermining, by the order controller, a particular classification fromamong a plurality of event classifications of a particular event fromamong the plurality of received events further comprises: determining,by the order controller the particular classification from among theplurality of event classifications comprising a read event and a writeevent.
 8. The method according to claim 1, further comprising:responsive to the order controller being ready to select a next event toprocess, determining whether a first status bit of a first next entryfrom among the plurality of entries in a first queue from among the atleast two queues and a second status bit of a second next entry fromamong the plurality of entries in a second queue from among the at leasttwo queues are both set to a done bit; responsive to both the firststatus bit and the second status bit being set to the done bit, then noentry is processed; responsive to both the first status bit and thesecond status bit not being set to the done bit, determining if only oneof the first status bit and the second status bit is set to an activebit; responsive to only one of the first status bit and the secondstatus bit being set to the active bit, selecting the next event toprocess from the particular event from among the first next entry andthe second next entry with particular event status bit set to the activebit; and responsive to both the first status bit and the second statusbit being set to the active bit, calculating, by the order controller,the exclusive OR of the first top bit of the first counter value and thesecond top bit of the second counter value and comparing the exclusiveOR value with comparator bit to determine whether to select the smalleror larger of a first remainder of bits of the first counter value and asecond remainder of bits of the second counter value as the oldestentry.
 9. The method according to claim 1, wherein comparing, by theorder controller, the exclusive OR value with a zero to determinewhether a first counter value in the first counter was stored before asecond counter value in the second counter further comprises: comparing,by the order controller, the exclusive OR value with the comparator bitto determine whether the first counter value was stored before thesecond counter value independent of a sequential order of the firstcounter value compared with the second counter value.
 10. The methodaccording to claim 1, wherein storing, by an order controller, each of aplurality of received events in a separate entry from among a pluralityof entries in one of at least two queues with a separate counter valueset from an arrival order counter at the time of storage, wherein thearrival order counter is incremented after storage of each of theplurality of received events and on overflow the arrival order counterwraps back to zero further comprises: selecting a number of bits of thearrival order counter to count to two times the sum of each depth of theat least two queues, wherein the top bit of the arrival order counterrepresents an overflow bit and where the other bits of the arrival ordercounter represent a remainder of bits.